Automatic Synthesis of Parsers and Validation of Bitstreams Within the MPEG Reconfigurable Video Coding Framework

Video coding technology has evolved in the past years into a variety of different and complex algorithms. So far the specifications of such standard algorithms have been done case by case, providing monolithic textual and reference software specifications, but without paying any attention to the possibility of further improvements of such monolithic standards. The MPEG Reconfigurable Video Coding (RVC) framework is a new ISO/IEC standard, currently under its final stage of development aiming at providing video codec specifications at the level of coding tools instead of monolithic descriptions. The possibility to select a subset of standard video coding algorithms to specify a decoder that satisfies application specific constraints is very attractive. However, such possibility to reconfigure codecs requires systematic procedures and tools capable of describing the new bitstream syntaxes of such new codecs. Moreover, it becomes also necessary to generate the associated parsers, capable of parsing the new bitstreams. This paper further explains the problem and describes the technologies used to describe new bitstream syntaxes. Additionally, the paper describes the methodologies and the tools for the validation of bitstream syntaxes descriptions as well as a systematic procedure for automatically synthesizing parsers from the bitstream description

Automatic Synthesis of Parsers and Validation of Bitstreams Within the MPEG Reconfigurable Video Coding Framework

International audienceVideo coding technology has evolved in the past years into a variety of different and complex algorithms. So far the specifications of such standard algorithms have been done case by case, providing monolithic textual and reference software specifications, but without paying any attention to the possibility of further improvements of such monolithic standards. The MPEG Reconfigurable Video Coding (RVC) framework is a new ISO/IEC standard, currently under its final stage of development aiming at providing video codec specifications at the level of coding tools instead of monolithic descriptions. The possibility to select a subset of standard video coding algorithms to specify a decoder that satisfies application specific constraints is very attractive. However, such possibility to reconfigure codecs requires systematic procedures and tools capable of describing the new bitstream syntaxes of such new codecs. Moreover, it becomes also necessary to generate the associated parsers, capable of parsing the new bitstreams. This paper further explains the problem and describes the technologies used to describe new bitstream syntaxes. Additionally, the paper describes the methodologies and the tools for the validation of bitstream syntaxes descriptions as well as a systematic procedure for automatically synthesizing parsers from the bitstream descriptions

Interface-based hierarchy for synchronous data-flow graphs

International audienceDataflow has proven to be an attractive computation model for programming digital signal processing (DSP) applications. A restricted version of dataflow, termed synchronous dataflow (SDF), offers strong compile-time predictability properties, but has limited expressive power. In this paper we propose a new type of hierarchy in the SDF domain allowing more expressivity while maintaining its predictability. This new hierarchy semantic is based on interfaces that fix the number of tokens consumed/produced by a hierarchical vertex in a manner that is independent or separate from the specified internal dataflow structure of the encapsulated subsystem. This interface-based hierarchy gives the application designer more flexibility in iterative construction of hierarchical representations, and experimentation with different optimization choices at different levels of the design hierarchy

Multi-Core Code Generation From Interface Based Hierarchy

International audienceDataflow has proved to be an attractive computational model for programming digital signal processing (DSP) applications. A restricted version of dataflow, termed synchronous dataflow (SDF), offers strong compile-time predictability properties, but has limited expressive power. A new type of hierarchy semantics that we propose for the SDF model allows more expressivity in SDF while maintaining its predictability. This new hierarchy semantic is based on interfaces that fix the number of tokens consumed/produced by a hierarchical vertex in a manner that is independent or separate from the specified internal dataflow structure of the encapsulated subsystem. This interface-based hierarchy gives the application designer more flexibility to apply iterative design approaches, and to make optimizing choices at the design level. This type of hierarchy is also closer to the host language semantics (i.e., the the semantics of the languages, such as C, Java and Verilog/VHDL, in which the internal functionality of primitive SDF blocks is typically written) because hierarchy levels can be interpreted as code closures (i.e., semantic boundaries), and allow one to design iterative patterns. This paper presents our proposed approach to hierarchical SDF system design, and demonstrates how we can take advantage of the proposed hierarchy semantics to generate efficient static C code targeting embedded applications

Validation of bitstream syntax and synthesis of parsers in the MPEG Reconfigurable Video Coding framework

International audienceVideo coding technology has evolved in the past years into a variety of different and complex algorithms. So far the specification of such standard algorithms has been done case by case providing monolithic textual and reference SW specifications, but without any attention on commonalities and the possibility of incremental improvements or modifications of such monolithic standards. The MPEG Reconfigurable Video Coding (RVC) framework is a new ISO standard, currently under development aiming at providing video codec specifications at the level of library functions instead of monolithic algorithms. The possibility to select a subset of standard coding algorithms to specify a decoder that satisfies application specific constraints is very attractive. However, such possibility to reconfigure codecs requires systematic procedures and tools capable of describing the new bitstream syntaxes of such new codecs. Moreover, it is also necessary to generate the associated parsers which are capable to parse the new bitstreams because they are not available "a priori" in the RVC library. This paper further explains the problem and describes the technologies used to describe new bitstream syntaxes within RVC. In addition, the paper describes the methodology and the tools for the validation of bitstream syntaxes descriptions as well as an example of systematic procedures for the direct synthesis of parsers in the same data flow formalism in which the RVC library component are implemented

Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation

International audienceThis paper proposes an automatic design flow from user-friendly design to efficient implementation of video processing systems. This design flow starts with the use of coarse-grain dataflow representations based on the CAL language, which is a complete language for dataflow programming of embedded systems. Our approach integrates previously developed techniques for detecting synchronous dataflow (SDF) regions within larger CAL networks, and exploiting the static structure of such regions using analysis tools in The Dataflow interchange format Package (TDP). Using a new XML format that we have developed to exchange dataflow information between different dataflow tools, we explore systematic implementation of signal processing systems using CAL, SDF-like region detection, TDP-based static scheduling, and CAL-to-C (CAL2C) translation. Our approach, which is a novel integration of three complementary dataflow tools -- the CAL parser, TDP, and CAL2C -- is demonstrated on an MPEG Reconfigurable Video Coding (RVC) decoder

Involvement of PPAR\u3b3 in the anticonvulsant activity of EP-80317, a ghrelin receptor antagonist

Ghrelin, des-acyl ghrelin and other related peptides possess anticonvulsant activities. Although ghrelin and cognate peptides were shown to physiologically regulate only the ghrelin receptor, some of them were pharmacologically proved to activate the peroxisome proliferator-activated receptor gamma (PPAR\u3b3) through stimulation of the scavenger receptor CD36 in macrophages. In our study, we challenged the hypothesis that PPAR\u3b3 could be involved in the anticonvulsant effects of EP-80317, a ghrelin receptor antagonist. For this purpose, we used the PPAR\u3b3 antagonist GW9662 to evaluate the modulation of EP-80317 anticonvulsant properties in two different models. Firstly, the anticonvulsant effects of EP-80317 were studied in rats treated with pilocarpine to induce status epilepticus (SE). Secondly, the anticonvulsant activity of EP-80317 was ascertained in the repeated 6-Hz corneal stimulation model in mice. Behavioral and video electrocorticographic (ECoG) analyses were performed in both models. We also characterized levels of immunoreactivity for PPAR\u3b3 in the hippocampus of 6-Hz corneally stimulated mice. EP-80317 predictably antagonized seizures in both models. Pre-treatment with GW9662 counteracted almost all EP-80317 effects both in mice and rats. Only the effects of EP-80317 on power spectra of ECoGs recorded during repeated 6-Hz corneal stimulation were practically unaffected by GW9662 administration. Moreover, GW9662 alone produced a decrease in the latency of tonic-clonic seizures and accelerated the onset of SE in rats. Finally, in the hippocampus of mice treated with EP-80317 we found increased levels of PPAR\u3b3 immunoreactivity. Overall, these results support the hypothesis that PPAR\u3b3 is able to modulate seizures and mediates the anticonvulsant effects of EP-80317

Detection chain and electronic readout of the QUBIC instrument

The Q and U Bolometric Interferometer for Cosmology (QUBIC) Technical Demonstrator (TD) aiming to shows the feasibility of the combination of interferometry and bolometric detection. The electronic readout system is based on an array of 128 NbSi Transition Edge Sensors cooled at 350mK readout with 128 SQUIDs at 1K controlled and amplified by an Application Specific Integrated Circuit at 40K. This readout design allows a 128:1 Time Domain Multiplexing. We report the design and the performance of the detection chain in this paper. The technological demonstrator unwent a campaign of test in the lab. Evaluation of the QUBIC bolometers and readout electronics includes the measurement of I-V curves, time constant and the Noise Equivalent Power. Currently the mean Noise Equivalent Power is ~ 2 x 10⁻¹⁶ W/√Hz

Detection chain and electronic readout of the QUBIC instrument

The Q and U Bolometric Interferometer for Cosmology (QUBIC) Technical Demonstrator (TD) aiming to shows the feasibility of the combination of interferometry and bolometric detection. The electronic readout system is based on an array of 128 NbSi Transition Edge Sensors cooled at 350mK readout with 128 SQUIDs at 1K controlled and amplified by an Application Specific Integrated Circuit at 40K. This readout design allows a 128:1 Time Domain Multiplexing. We report the design and the performance of the detection chain in this paper. The technological demonstrator unwent a campaign of test in the lab. Evaluation of the QUBIC bolometers and readout electronics includes the measurement of I-V curves, time constant and the Noise Equivalent Power. Currently the mean Noise Equivalent Power is ~ 2 x 10⁻¹⁶ W/√Hz